Pratik Kotkar, William Thies, and Saman Amarasinghe. An Audio Wiki for Building Local Repositories of Knowledge in the Developing World. In Wireless Systems: Advanced Research and Development (Poster Session), Bangalore, India, January, 2008. (Paper: PDF; BibTeX)

Xin David Zhang, Qiuyuan J. Li, Rodric Rabbah, and Saman Amarasinghe. A Lightweight Streaming Layer for Multicore Execution. In 2007 Workshop on Design, Architecture and Simulation of Chip Multi-Processors, Chicago, IL, December, 2007. (Paper: PDF; BibTeX)

William Thies, Vikram Chandrasekhar, and Saman Amarasinghe. A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. In Proceedings of the 40th International Symposium on Microarchitecture, Chicago, IL, December, 2007. (Paper: PDF; Talk: PDF, PPT; BibTeX)

Qin Zhao, Rodric Rabbah, Saman Amarasinghe, Larry Rudolph, and Weng-Fai Wong. Ubiquitous Memory Introspection. In 2007 International Symposium on Code Generation and Optimization (CGO), San Jose, CA, March, 2007. (Paper: PDF, PS; BibTeX)

Michael Gordon, William Thies, and Saman Amarasinghe. Exploiting Coarse-Grained Task, Data, and Pipeline Parallelism in Stream Programs. In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October, 2006. (Paper: PDF; Talk: PDF, PPT; BibTeX)

William Thies, John Paul Urbanski, Todd Thorsen, and Saman Amarasinghe. Abstraction Layers for Scalable Microfluidic Biocomputers. In Proceedings of the 12th International Meeting on DNA Computing, Seoul, Korea, June, 2006. (Paper: PDF; Talk: PDF, PPT; BibTeX)

Matthew Drake, Henry Hoffman, Rodric Rabbah, and Saman Amarasinghe. MPEG-2 Decoding in a Stream Programming Language. In 20th IEEE International Parallel & Distributed Processing Symposium, Rhodes Island, Greece, April, 2006. (Paper: PDF, PS; Talk: PPT; BibTeX)

Samuel Larsen, Rodric Rabbah, and Saman Amarasinghe. Exploiting Vector Parallelism in Software Pipelined Loops. In Proceedings of the 38th International Symposium on Microarchitecture, Barcelona, Spain, November, 2005. (Paper: PDF; BibTeX)

Sitij Agrawal, William Thies, and Saman Amarasinghe. Optimizing Stream Programs Using Linear State Space Analysis. In Proceeedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, San Francisco, CA, September, 2005. (Paper: PDF, PS; Talk: PDF, PPT; BibTeX)

Jiawen Chen, Michael Gordon, William Thies, Matthias Zwicker, Kari Pulli, and Fredo Durand. A Reconfigurable Architecture for Load-Balanced Rendering. In Graphics Hardware, Los Angeles, CA, August, 2005. (Paper: PDF; Talk: PDF, PPT; BibTeX)

William Thies, Michal Karczmarek, Janis Sermulins, Rodric Rabbah, and Saman Amarasinghe. Teleport Messaging for Distributed Stream Programs. In ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming, Chicago, Illinois, June, 2005. (Paper: PDF; Talk: PDF, PPT; BibTeX)

Janis Sermulins, William Thies, Rodric Rabbah, and Saman Amarasinghe. Cache Aware Optimization of Stream Programs. In Proceedings of the 2005 Conference on Languages, Compilers, and Tools for Embedded Systems, Chicago, June, 2005. (Paper: PDF, PS; Talk: PPT; BibTeX)

Saman Amarasinghe. Multicores from the Compiler's Perspective: A Blessing or A Curse?. In Proceedings of the 3rd International Symposium on Code Generation and Optimization, San Jose, California, March, 2005. (Paper: PDF; Talk: PDF, PPT; BibTeX)

Derek Bruening and Saman Amarasinghe. Maintaining Consistency and Bounding Capacity of Software Code Caches. In Proceedings of the 3rd International Symposium on Code Generation and Optimization, San Jose, California, March, 2005. (Paper: PDF, PS; BibTeX)

Mark Stephenson and Saman Amarasinghe. Predicting Unroll Factors Using Supervised Classification. In Proceedings of the 3rd International Symposium on Code Generation and Optimization, San Jose, California, March, 2005. (Paper: PDF, PS; BibTeX)

Kimberly Kuo, Rodric Rabbah, and Saman Amarasinghe. A Productive Programming Environment for Stream Computing. In Second Workshop on Productivity and Performance in High-End Computing, San Francisco, February 13, 2005, pp. 35-44. (Paper: PDF; BibTeX)

Michael Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Benjamin Greenwald, Henry Hoffman, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman Amarasinghe, and Anant Agarwal. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In Proceedings of the 31st Annual International Symposium on Computer Architecture, Munich, Germany, June, 2004. (Paper: PDF, PS; BibTeX)

Gleb A. Chuvpilo and Saman Amarasinghe. High-Bandwidth Packet Switching on the Raw General-Purpose Architecture. In Proceedings of the International Conference on Parallel Processing (ICPP-03), Kaohsiung, Taiwan, Republic of China, October 6, 2003. (Paper: PDF; BibTeX)

Diego Puppin, Mark Stephenson, Saman Amarasinghe, Una-May O'Reilly, and Martin C. Martin. Adapting Convergent Scheduling Using Machine Learning. In Proceedings of the 16th International Workshop on Languanges and Compilers for Parallel Computing, College Station, TX, October 2, 2003. (Paper: PDF; Talk: PPT; BibTeX)

Gregory Sullivan, Derek Bruening, Iris Baron, Timothy Garnett, and Saman Amarasinghe. Dynamic Native Optimization of Interpreters. In Proceedings of the ACM SIGPLAN 2003 Workshop on Interpreters, Virtual Machines and Emulators, San Diego, California, June, 2003. (Paper: PDF; BibTeX)

Andrew A. Lamb, William Thies, and Saman Amarasinghe. Linear Analysis and Optimization of Stream Programs. In Proceedings of the SIGPLAN '03 Conference on Programming Language Design and Implementation, San Diego, CA, June, 2003. (Paper: PDF, PS; Talk: PPT; BibTeX)

Mark Stephenson, Saman Amarasinghe, Martin C. Martin, and Una-May O'Reilly. Meta Optimization: Improving Compiler Heuristics with Machine Learning. In Proceedings of the SIGPLAN '03 Conference on Programming Language Design and Implementation, San Diego, CA, June, 2003. (Paper: PDF, PS; BibTeX)

Michal Karczmarek, William Thies, and Saman Amarasinghe. Phased Scheduling of Stream Programs. In Proceedings of the 2003 Conference on Languages, Compilers, and Tools for Embedded Systems, San Diego, CA, June, 2003. (Paper: PDF, PS; Talk: PPT; BibTeX)

Mark Stephenson, Una-May O'Reilly, Martin C. Martin, and Saman Amarasinghe. Genetic Programming Applied to Compiler Heuristic Optimization. In Proceedings of the 6th European Conference on Genetic Programming, Essex, UK, April 14, 2003. (Paper: PDF, PS; Talk: PPT; BibTeX)

Saman Amarasinghe. Defying the Speed of Light: Wire-Exposed Architectures and Spatially-Aware Compilers. In 28th Annual GOMACTech Conference, Tampa, Florida, March, 2003. (Paper: PDF; BibTeX)

Derek Bruening, Timothy Garnett, and Saman Amarasinghe. An Infrastructure for Adaptive Dynamic Optimization. In Proceedings of the 1st International Symposium on Code Generation and Optimization, San Francisco, March, 2003. (Paper: PDF, PS; BibTeX)

Michael Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Scalar Operand Networks: On-chip Interconnect for ILP in Partitioned Architectures. In Proceedings of the Ninth International Symposium on High Performance Computer Architecture, Anaheim, California, February, 2003. (Paper: PDF; BibTeX)

Walter Lee, Diego Puppin, Shane Michael Swenson, and Saman Amarasinghe. Convergent Scheduling. In Proceedings of the 35th International Symposium on Microarchitecture, Istanbul, Turkey, November, 2002. (Paper: PDF, PS; BibTeX)

Michael Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Christopher Leger, Andrew A. Lamb, Jeremy Wong, Henry Hoffman, David Z. Maze, and Saman Amarasinghe. A Stream Compiler for Communication-Exposed Architectures. In ASPLOS 2002, San Jose, CA USA, October, 2002. (Paper: PDF, PS; Talk: PPT; BibTeX)

Samuel Larsen, Emmett Witchel, and Saman Amarasinghe. Increasing and Detecting Memory Address Congruence. In Proceedings of the 11th International Conference on Parallel Architectures and Compilation Techniques, Charlottesville, VA, September, 2002. (Paper: PDF, PS; BibTeX)

Vladimir Kiriansky, Derek Bruening, and Saman Amarasinghe. Secure Execution Via Program Shepherding. In Proceedings of the 11th USENIX Security Symposium, San Francisco, August 5, 2002. (Paper: PDF, PS; BibTeX)

William Thies, Michal Karczmarek, Michael Gordon, David Z. Maze, Jeremy Wong, Henry Hoffman, Matthew Brown, and Saman Amarasinghe. A Common Machine Language for Grid-Based Architectures. In ACM SIGARCH Computer Architecture News, June, 2002. (Paper: PDF, PS; BibTeX)

Libby Levison, William Thies, and Saman Amarasinghe. Providing Web Search Capability for Low-Connectivity Communities. In 2002 International Symposium on Technology and Society, Raleigh, North Carolina, June, 2002. (Paper: PDF; BibTeX)

William Thies, Janelle Prevost, Tazeen Mahtab, Genevieve T. Cuevas, Saad Shakhshir, Alexandro Artola, Binh D. Vo, Yuliya Litvak, Sheldon Chan, Sid Henderson, Mark Halsey, Libby Levison, and Saman Amarasinghe. Searching the World Wide Web in Low-Connectivity Communities. In 11th International World Wide Web Conference, Global Community Track, Honolulu, Hawaii, May, 2002. (Paper: PDF; Talk: PPT; BibTeX)

Darin Petkov, Randolph Harr, and Saman Amarasinghe. Efficient Pipelining of Nested Loops: Unroll-and-Squash. In 16th International Parallel and Distributed Processing Symposium, Fort Lauderdale, Florida, April, 2002. (Paper: PDF; BibTeX)

William Thies, Michal Karczmarek, and Saman Amarasinghe. StreamIt: A Language for Streaming Applications. In Proceedings of the 2002 International Conference on Compiler Construction, Grenoble, France, April, 2002. (Paper: PDF, PS; Talk: PPT; BibTeX)

Gleb A. Chuvpilo, David Wentzlaff, and Saman Amarasinghe. Gigabit IP Routing on Raw. In Proceedings of the 1st HPCA Workshop on Network Processors, Cambridge, Massachusetts, February, 2002, pp. 2-9. (Paper: PDF, PS; BibTeX)

Emmett Witchel, Samuel Larsen, C. Scott Ananian, and Krste Asanovic. Direct Address Caches for Reduced Power Consumption. In Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, December, 2001, pp. 124-133. (Paper: PDF; BibTeX)

Diego Puppin and Dean Tullsen. Maximizing TLP with Loop-Parallelization on SMT. In Proceedings of the 5th Workshop on Multithreaded Execution, Architecture, and Compilation, Austin, Texas, December, 2001. (Paper: PS; BibTeX)

Derek Bruening, Evelyn Duesterwald, and Saman Amarasinghe. Design and Implementation of a Dynamic Optimization Framework for Windows. In Proceedings of the 4th ACM Workshop on Feedback-Directed and Dynamic Optimization, Austin, Texas, December, 2001. (Paper: PDF, PS; BibTeX)

Jeffrey W. Sheldon, Walter Lee, Benjamin Greenwald, and Saman Amarasinghe. Strength Reduction of Integer Divison and Modulo Operations. In Proceedings of the '01 Conference on Languages and Compilers for Parallel Computing, Cumberland Falls, Kentucky, August, 2001. (Paper: PDF, PS; BibTeX)

Libby Levison, William Thies, and Saman Amarasinghe. The TEK Search Engine. In Development by Design Workshop, Boston, MA, July, 2001. (Paper: PDF; BibTeX)

William Thies, Frederic Vivien, Jeffrey W. Sheldon, and Saman Amarasinghe. A Unified Framework for Schedule and Storage Optimization. In Proceedings of the SIGPLAN '01 Conference on Programming Language Design and Implementation, Snowbird, Utah, June, 2001. (Paper: PDF, PS; Talk: PDF; BibTeX)

Derek Bruening, Srikrishna Devabhaktuni, and Saman Amarasinghe. Softspec: Software-based Speculative Parallelism. In Proceedings of the 3rd ACM Workshop on Feedback-Directed and Dynamic Optimization, Monterey, California, December, 2000. (Paper: PDF, PS; BibTeX)

Csaba Andras Moritz, Matthew Frank, and Saman Amarasinghe. FlexCache: A Framework for Flexible Compiler Generated Data Caching. In Proceedings of the 2nd Workshop on Intelligent Memory Systems, Boston, Massachusetts, November, 2000. (Paper: PDF, PS; BibTeX)

Samuel Larsen and Saman Amarasinghe. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. In Proceedings of the SIGPLAN '00 Conference on Programming Language Design and Implementation, Vancouver, British Columbia, June, 2000. (Paper: PDF, PS; BibTeX)

Mark Stephenson, Johnathan Babb, and Saman Amarasinghe. Bitwidth Analysis with Application to Silicon Compilation. In Proceedings of the SIGPLAN '00 Conference on Programming Language Design and Implementation, Vancouver, British Columbia, June, 2000. (Paper: PDF, PS; BibTeX)

Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Maps: A Compiler-Managed Memory System for Raw Machines. In Proceedings of the 26th International Conference on Computer Architecture, Atlanta, Georgia, May, 1999. (Paper: PDF, PS; BibTeX)

Johnathan Babb, Martin Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe. Parallelizing Applications into Silicon. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Napa Valley, California, April, 1999. (Paper: PDF, PS; BibTeX)

Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Memory Bank Disambiguation using Modulo Unrolling for Raw Machines. In Proceedings of the Fifth International Conference on High Performance Computing, December, 1998. (Paper: PDF, PS; BibTeX)

Walter Lee, Rajeev Barua, Matthew Frank, Srikrishna Devabhaktuni, Johnathan Babb, Vivek Sarkar, and Saman Amarasinghe. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. In Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, October, 1998. (Paper: PDF, PS; BibTeX)

Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna, and Michael Taylor. The Raw Compiler Project. In Proceedings of the Second SUIF Compiler Workshop, Stanford, California, August, 1997. (Paper: PDF, PS; BibTeX)

John Paul Urbanski, William Thies, Christopher Rhodes, Saman Amarasinghe, and Todd Thorsen. Digital microfluidics using soft lithography. In Lab on a Chip, January, 2006, pp. 96-104. (Paper: PDF; BibTeX)

Diego Puppin, Mark Stephenson, Walter Lee, and Saman Amarasinghe. Convergent Scheduling. In Journal of Instruction-Level Parallelism, September, 2005. (Paper: PDF; BibTeX)

Michael Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Benjamin Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman Amarasinghe, and Anant Agarwal. The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. In IEEE Micro, May, 2002. (Paper: PDF; BibTeX)

Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Compiler Support for Scalable and Efficient Memory Systems. In Transactions on Computers, November, 2001. (Paper: PDF, PS; BibTeX)

Elliot L. Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Johnathan Babb, Saman Amarasinghe, and Anant Agarwal. Baring it all to Software: Raw Machines. In IEEE Computer, September, 1997. (Paper: PDF, PS; BibTeX)

Saman Amarasinghe. The Looming Software Crisis due to the Multicore Menace. Presented at the CISE Distinguished Lecture, National Science Foundation, Washington D. C., February, 2007. (Talk: PDF, PPT; BibTeX)

Saman Amarasinghe. StreamIt – A Programming Language for the Era of Multicores. Presented at the Distinguished Lecture, Department of Computer Science, University of Alberta, Edmonton, Alberta, Canada, November, 2006. (Talk: PDF, PPT; BibTeX)

William Thies, John Paul Urbanski, Todd Thorsen, and Saman Amarasinghe. Abstraction layers for scalable microfluidic biocomputers (Extended version). MIT/CSAIL Technical Report MIT-CSAIL-TR-2006-034, May, 2006. (Paper: PDF; BibTeX)

Vladimir Kiriansky, Derek Bruening, and Saman Amarasinghe. Execution Model Enforcement Via Program Shepherding. MIT/LCS Technical Memo LCS-TM-638, May, 2003. (Paper: PDF, PS; BibTeX)

Michael Gordon, William Thies, Michal Karczmarek, Jeremy Wong, Henry Hoffman, David Z. Maze, and Saman Amarasinghe. A Stream Compiler for Communication-Exposed Architectures. MIT/LCS Technical Memo LCS-TM-627 (Older versions available here), May, 2002. (Paper: PDF, PS; BibTeX)

Vladimir Kiriansky, Derek Bruening, and Saman Amarasinghe. Secure Execution Via Program Shepherding. MIT/LCS Technical Memo LCS-TM-625, February, 2002. (Paper: PDF, PS; BibTeX)

William Thies, Michal Karczmarek, Michael Gordon, David Z. Maze, Jeremy Wong, Henry Hoffman, Matthew Brown, and Saman Amarasinghe. StreamIt: A Compiler for Streaming Applications. MIT/LCS Technical Memo LCS-TM-622, December, 2001. (Paper: PDF, PS; BibTeX)

Samuel Larsen, Emmett Witchel, and Saman Amarasinghe. Techniques for Increasing and Detecting Memory Alignment. MIT/LCS Technical Memo LCS-TM-621, November, 2001. (Paper: PDF, PS; BibTeX)

William Thies, Michal Karczmarek, and Saman Amarasinghe. StreaMIT: A Language for Streaming Applications. MIT/LCS Technical Memo LCS-TM-620, August, 2001. (Paper: PDF, PS; BibTeX)

Govinda Shrestha and Saman Amarasinghe. Perspectives on the Use of Internet in Sri Lanka. MIT/LCS Technical Report LCS-TR-815, January, 2001. (Paper: PDF; BibTeX)

William Thies, Frederic Vivien, Jeffrey W. Sheldon, and Saman Amarasinghe. A Unified Framework for Schedule and Storage Optimization. MIT/LCS Technical Memo LCS-TM-613, November, 2000. (Paper: PDF, PS; BibTeX)

Derek Bruening, Srikrishna Devabhaktuni, and Saman Amarasinghe. Softspec: Software-Based Speculative Parallelism. MIT/LCS Technical Memo LCS-TM-606, April, 2000. (Paper: PDF, PS; BibTeX)

Mark Stephenson, Johnathan Babb, and Saman Amarasinghe. Bitwidth Analysis with Application to Silicon Compilation. MIT/LCS Technical Memo LCS-TM-602, November, 1999. (Paper: PDF, PS; BibTeX)

Samuel Larsen and Saman Amarasinghe. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. MIT/LCS Technical Memo LCS-TM-601, November, 1999. (Paper: PDF, PS; BibTeX)

Walter Lee, Benjamin Greenwald, and Saman Amarasinghe. Strength Reduction of Integer Division and Modulo Operations. MIT/LCS Technical Memo LCS-TM-600, November, 1999. (Paper: PDF, PS; BibTeX)

Csaba Andras Moritz, Matthew Frank, Walter Lee, and Saman Amarasinghe. Hot Pages: Software Caching for Raw Microprocessors. MIT/LCS Technical Memo LCS-TM-599, August, 1999. (Paper: PDF, PS; BibTeX)

Matthew Frank, Csaba Andras Moritz, Benjamin Greenwald, Saman Amarasinghe, and Anant Agarwal. SUDS: Primitive Mechanisms for Memory Dependence Speculation. MIT/LCS Technical Memo LCS-TM-591, January, 1999. (Paper: PDF, PS; BibTeX)

Johnathan Babb, Martin Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe. Parallelizing Applications into Smart Memories. MIT/LCS Technical Report LCS-TR-769, October, 1998. (BibTeX)

Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Maps: A Compiler-Managed Memory System for Raw Machines. MIT/LCS Technical Memo LCS-TM-583, July, 1998. (BibTeX)

Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal. Memory Bank Disambiguation using Modulo Unrolling for Raw Machines. MIT/LCS Technical Report LCS-TR-759, June, 1998. (Paper: PDF, PS; BibTeX)

Walter Lee, Rajeev Barua, Devabhaktuni Srikrishna, Johnathan Babb, Vivek Sarkar, Saman Amarasinghe, and Anant Agarwal. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. MIT/LCS Technical Memo LCS-TM-572, December, 1997. (Paper: PDF, PS; BibTeX)

Elliot L. Waingold, Michael Taylor, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Srikrishna Devabhaktuni, Rajeev Barua, Johnathan Babb, Saman Amarasinghe, and Anant Agarwal. Baring it all to Software: The Raw Machine. MIT/LCS Technical Report LCS-TR-709, March, 1997. (Paper: PDF, PS; BibTeX)

Xin David Zhang. A Streaming Computation Framework for the Cell Processor. M.Eng. Thesis, Massachusetts Institute of Technology, August, 2007. (Paper: PDF; BibTeX)

Abdulbasier Aziz. Image-Based Motion Estimation in a Stream Programming Language. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2007. (Paper: PDF; BibTeX)

Sie Hendrata Dharmawan. Understanding Program Structure and Behavior. M.Eng. Thesis, Massachusetts Institute of Technology, May, 2006. (Paper: PDF, PS; BibTeX)

Mark Stephenson. Automating the Construction of Compiler Heuristics Using Machine Learning. Ph.D. Thesis, Massachusetts Institute of Technology, May, 2006. (Paper: PDF; BibTeX)

Matthew Drake. Stream Programming for Image and Video Compression. M.Eng. Thesis, Massachusetts Institute of Technology, May, 2006. (Paper: PDF, PS; BibTeX)

Samuel Larsen. Compilation Techniques for Short-Vector Instructions. Ph.D. Thesis, Massachusetts Institute of Technology, April, 2006. (Paper: PDF, PS; BibTeX)

Janis Sermulins. Cache Optimizations for Stream Programs. M.Eng. Thesis, Massachusetts Institute of Technology, May, 2005. (Paper: PDF, PS; BibTeX)

Derek Bruening. Efficient, Transparent, and Comprehensive Runtime Code Manipulation. Ph.D. Thesis, Massachusetts Institute of Technology, September, 2004. (Paper: PDF, PS; BibTeX)

Sitij Agrawal. Linear State-Space Analysis and Optimization of StreamIt Programs. M.Eng. Thesis, Massachusetts Institute of Technology, August, 2004. (Paper: PDF; BibTeX)

Juan C Reyes. A Graph Editing Framework for the StreamIt Language. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2004. (Paper: PDF, PS; BibTeX)

Kimberly Kuo. The StreamIt Development Tool: A Programming Environment for StreamIt. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2004. (Paper: PDF, PS; BibTeX)

Christopher Leger. An API for Dynamic Partial Evaluation under DynamoRIO. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2004. (Paper: PDF, PS; BibTeX)

Jeremy Wong. Modeling the Scalability of Acyclic Stream Programs. M.Eng. Thesis, Massachusetts Institute of Technology, January, 2004. (Paper: PDF; BibTeX)

Iris Baron. Dynamic Optimization of Interpreters using DynamoRIO. S.M. Thesis, Massachusetts Institute of Technology, September, 2003. (Paper: PDF, PS; BibTeX)

Timothy Garnett. Dynamic Optimization of IA-32 Applications Under DynamoRIO. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2003. (Paper: PDF; BibTeX)

Andrew A. Lamb. Linear Analysis and Optimization of Stream Programs. M.Eng. Thesis, Massachusetts Institute of Technology, May, 2003. (Paper: PDF, PS; BibTeX)

Matthew Frank. SUDS: Automatic Parallelization for Raw Processors. Ph.D. Thesis, Massachusetts Institute of Technology, May, 2003. (Paper: PDF; BibTeX)

Vladimir Kiriansky. Secure Execution Environment via Program Shepherding. M.Eng. Thesis, Massachusetts Institute of Technology, February, 2003. (Paper: PDF, PS; BibTeX)

Michal Karczmarek. Constrained and Phased Scheduling of Synchronous Data Flow Graphs for StreamIt Language. S.M. Thesis, Massachusetts Institute of Technology, December, 2002. (Paper: PDF, PS; BibTeX)

Diego Puppin. Convergent Scheduling: A Flexible and Extensible Scheduling Framework for Clustered VLIW Architectures. S.M. Thesis, Massachusetts Institute of Technology, December, 2002. (Paper: PDF, PS; BibTeX)

Samidh Chakrabarti. Low-Bandwidth Web Access with Tandem Proxies. M.Eng. Thesis, Massachusetts Institute of Technology, September, 2002. (Paper: PDF, PS; BibTeX)

Gleb A. Chuvpilo. High-Bandwidth Packet Switching on the Raw General-Purpose Architecture. S.M. Thesis, Massachusetts Institute of Technology, August, 2002. (Paper: PDF; BibTeX)

Michael Gordon. A Stream-Aware Compiler for Communication-Exposed Architectures. S.M. Thesis, Massachusetts Institute of Technology, August, 2002. (Paper: PDF, PS; BibTeX)

William Thies. A Unified Framework for Schedule and Storage Optimization. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2002. (Paper: PDF, PS; BibTeX)

Shane Michael Swenson. Spatial Instruction Scheduling for Raw Machines. M.Eng. Thesis, Massachusetts Institute of Technology, February, 2002. (Paper: PS; BibTeX)

David Z. Maze. A Flexible Compilation Infrastructure for VLIW and SIMD Architectures. M.Eng. Thesis, Massachusetts Institute of Technology, September, 2001. (Paper: PDF, PS; BibTeX)

Mathew Deeds. Design and Implementation of a PowerPC and AltiVec Backend with Optimization. M.Eng. Thesis, Massachusetts Institute of Technology, September, 2001. (Paper: PDF; BibTeX)

Jeffrey W. Sheldon. Strength Reduction of Integer Division and Modulo Operations. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2001. (Paper: PS; BibTeX)

Darin Petkov. Efficient Pipelining of Nested Loops: Unroll-and-Squash. M.Eng. Thesis, Massachusetts Institute of Technology, February, 2001. (Paper: PDF; BibTeX)

Elliot L. Waingold. SIFt: A Compiler for Streaming Applications. M.Eng. Thesis, Massachusetts Institute of Technology, June, 2000. (Paper: PDF, PS; BibTeX)

Mark Stephenson. Bitwise: Optimizing Bitwidths Using Data-Range Propagation. S.M. Thesis, Massachusetts Institute of Technology, May, 2000. (Paper: PDF, PS; BibTeX)

Samuel Larsen. Exploiting Superword Level Parallelism with Multimedia Instruction Sets. S.M. Thesis, Massachusetts Institute of Technology, May, 2000. (Paper: PDF, PS; BibTeX)

Rajeev Barua. Maps: A Compiler-Managed Memory System for Software-Exposed Architectures. Ph.D. Thesis, Massachusetts Institute of Technology, January, 2000. (Paper: PDF, PS; BibTeX)

Benjamin Greenwald. A Technique for Compilation to Exposed Memory Hierarchy. S.M. Thesis, Massachusetts Institute of Technology, September, 1999. (Paper: PDF, PS; BibTeX)

Tsvetomir P. Petrov. Code Compaction and Parallelization for VLIW/DSP Chip Architectures. M.Eng. Thesis, Massachusetts Institute of Technology, June, 1999. (Paper: PDF, PS; BibTeX)

Tyler J. Moeller. Field Programmable Gate Arrays for Radar Front-End Digital Signal Processing. M.Eng. Thesis, Massachusetts Institute of Technology, May, 1999. (Paper: PDF, PS; BibTeX)

Srikrishna Devabhaktuni. Softspec: Software-based Speculative Parallelism via Stride Prediction. S.M. Thesis, Massachusetts Institute of Technology, 1999. (Paper: PDF, PS; BibTeX)